An Efficient Hybrid Decoder for Block Turbo Codes

Memory-efficient Turbo Decoder Architectures for Ldpc Codes

In this paper, we propose a turbo decoding messagepassing (TDMP) algorithm to decode regular and irregular lowdensity parity-check (LDPC) codes. The TDMP algorithm has two main advantages over the commonly employed two-phase messagepassing algorithm. First, it exhibits a faster convergence behavior (up to 50% less iterations), and improvement in coding gain (up to an order of magnitude for mode...

Low Complexity Decoder for CCSDS Turbo codes

Error correction codes are a means of including redundancy in a stream of information bits to allow the detection and correction of symbol errors during transmission. In Forward Error Correction (FEC) it is desirable to have low Bit Error Rates (BER) and low decoder complexity for reliable data transmission Turbo code is a great achievement in the field of communication system. Turbo code also ...

A Low Complexity Block Turbo Decoder Architecture

We present a low-complexity architecture designed for the decoding of block turbo codes. In particular we simplify the implementation of Pyndiah’s algorithm by not memorizing any of the concurrent codewords generated by the Chase search.

Decoding of Block Turbo Codes

Inter-Block Permuted Turbo Codes

The structure and size of the interleaver used in a turbo code critically affect the distance spectrum and the covariance property of a component decoder’s information input and soft output. This paper introduces a new class of interleavers, the inter-block permutation (IBP) interleavers, that can be build on any existing “good” block-wise interleaver by simply adding an IBP stage. The IBP inte...